Modern high speed data communications receivers must be capable of processing input signals that are severely impaired due to the properties of the transmission channel, for example, input signals that are impaired by frequency-dependent loss in copper backplanes or dispersion in optical fibers. Digital signal processing enables a high speed data communications receiver to adapt to a particular channel that it is paired with, by sampling and quantizing input data received at the high speed data communications receiver utilizing an ADC.
High speed ADCs, such as CMOS flash ADCs, must be area and power-efficient. As a result, high speed ADCs typically exhibit large inherent voltage offsets that require initial calibration. A prior art method of calibrating a high speed ADC utilizes a digital-to-analog converter (DAC) to calibrate a high speed ADC.
FIG. 1 illustrates an example of a known arrangement for calibrating a high speed ADC 100 that is driven by an ADC driver 110. In the arrangement shown in FIG. 1, the ADC 100 is located in a serial data communications receiver and the ADC 100 is calibrated by a calibration circuit 120 that includes a DAC 130.
The ADC driver 110 has two modes of operation, an ADC calibration mode and an ADC operation mode. When the ADC driver 110 is operating in the ADC operation mode, the low output impedance of the ADC driver 110 inhibits the development of error currents. However, when the ADC driver 110 is operating in the ADC calibration mode, only a relatively high output resistance of the DAC 130 is present at the input the ADC 100, such that the ADC driver 110 is effectively not in operation in the ADC calibration mode.
To reduce the total voltage error, a DAC 130 with a lower unit resistance R may be used. However, there are practical limits to this approach because for a given accuracy, smaller value resistors require more chip area. Further, utilizing a DAC 130 with a lower unit resistance R leads to higher DAC supply currents and, consequently, high voltage drops across the power nets, thereby causing further errors. The industry trend is for gate lengths to shrink with new silicon fabrication processes, and for ADC resolutions to go up. On the one hand, calibration errors go up as ADC drivers and ADCs grow in size due to increases in ADC driver leakage current and ADC kick-back charge. On the other hand, error tolerance of the ADC goes down as the resolution of the ADC is increased.
Improvements in calibration circuits for ADCs are therefore desirable.